Abstract
Nondestructive analysis of ASIC (Application Specific Integrated Circuit) components, in their early engineering evaluation stage, can assist in discovering the inadequately defined design rules by the IC production foundry FABs, as well as revealing unintentional violations of layout rules and guidelines introduced by the layout engineers during the formation of the chip’s layout.In this work we present the implementation of the PEM (Photon Emission Microscopy) techniques as a part of the evaluation of the circuits/blocks which are designed internally by SanDisk engineers or externally by IP (Intellectual Property) vendors. This concept which is applied at the test chip level, is demonstrated via two test cases.
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