Reusable intellectual property cores in PC data protection ASIC design

Abstract

This paper presents how we use a soft Peripheral Component Interconnect (PCI) Intellectual Property (IP) for converting an Industry Standard Architecture (ISA) bus to a PCI bus in the personal computer (PC) data protection application specific integrated circuit (ASIC) design. To save design time and achieve a more efficient design, we use a verified PCI IP. The PCI IP was a soft IP and designed by Pheonix Technology. The total blocks consist of 3 major blocks: PCI IP block, user interface block, and PC data protection block. We verified the functioning of the PC data protection circuit with a supplied test environment by Pheonix Technology. So we built in a test environment easily. We cooperated with the ASIC foundry and IP vendor for IP integration using PCI IP. The operating frequency is 33 MHz. The size of EEPROM is 64 Kbytes and the size of the data bus is 32 bits. We fabricated the chip in a 0.5 /spl mu/m CMOS technology since the EEPROM was made by 0.5 /spl mu/m CMOS technology.