Detailed Modeling and In-Situ Calorimetric Verification of Three-Phase Sparse NPC Converter Power Semiconductor Losses

Abstract

The three-phase three-level (3-L) Sparse Neutral Point Clamped Converter (SNPCC) combines a 3-L matrix stage and a three-phase two-level inverter stage to generate 3-L switched output voltages with a reduced transistor count (10 instead of 12 or 18) compared to the classical 3-L NPCC or 3-L active NPCC structure, targeting variable-speed drive systems with low ripple of the motor phase currents or bidirectional three-phase PFC rectifier systems with reduced boost inductor volume. This paper analyzes and experimentally characterizes the performance of an IGBT-based three-phase 3-L SNPCC converter, and describes for the first time a hybrid current commutation effect between inverter-stage diodes and matrix-stage IGBTs that occurs when operating with lower modulation indices and leads to increased switching losses (up to 20%). The proposed new semiconductor loss modeling approach accounts for this effect successfully, which is verified (< 10% error) on an 800V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dc</sub> , 7.5kW SNPCC hardware demonstrator using a new in-situ calorimetric method that facilitates accurate stage-level semiconductor loss measurements. Heat spreading effects caused by the asymmetrical losses injection and thermal decoupling between two in-situ loss measurement blocks are carefully checked with FEM simulations. Further, an experimental evaluation of common-mode and differential-mode high-frequency voltage-time area ripples (as a generic measure for the required filtering effort) for three typical symmetrical and asymmetrical modulation switching state sequences is provided together with the semiconductor loss characterization. Utilizing a low-switching-loss asymmetric modulation scheme that operates the 3-L matrix stage and the 2-L inverter stage with effective switching frequencies of 16kHz and 5.3kHz, respectively, the 3-L SNPCC demonstrator finally achieves a high rated-power (7.5kW, load current phase shift ϕ = 0) semiconductor efficiency of 98.8%.