Abstract
Phase Locked Loop (PLL) is a feedback system that is configured as frequency multipliers, tracking generators, demodulators and clock recovery circuits. Today the most challenging requirement engineers' face is design of fast locking PLL with low jitter. Many analog techniques are proposed to fulfill the demand but they result in increasing complexity of design and long lock in time. In this paper, review of advantages of an All-Digital phase locked loop (ADPLL) over an analog phase locked loop (APLL) in terms of stability, programmability is studied. Various approaches to design the blocks of ADPLL till now adopted are presented in this paper.
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