Abstract
The Phase-Locked Loop (PLL) is a feedback system used for the synchronization of signals in terms of frequency and phase. It is configured in digital communication, Bluetooth, mobile transmitter, etc. Many analog and mixed techniques have already been proposed with the advancement in time, but design time is much more for that. An ADPLL implements all the major blocks of the PLL in the digital form. The most challenging task is to design a fast locking ADPLL with a small area and low jitter. In this paper, a detailed study of each block of ADPLL architecture is presented and what changes were incurred in these blocks with the advancement in the research and their pros and cons. The comparison of best ADPLL in terms of their parameters and the techniques used in them is discussed.
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