Designing customized ISA processors using high level synthesis

Abstract

In this paper we propose a new degree of flexibility for soft processor design in which only the instructions relevant to the task at hand are implemented as a subset of the Instruction Set Architecture (ISA). These customized processors execute software kernels in the usual way, yet can be implemented with a fraction of the hardware resources used by other full- ISA soft processor cores. We present a design methodology for such customized ISA processors where the functional description of the processor is written in a high level language and the hardware implementation is obtained using high level synthesis (HLS) tools. We investigate the potential and limitations of the HLS tools to take processor simulator-like implementations in C/C++ and produce functional hardware processor architectures. We apply this methodology to two relevant applications -a basic linear algebra application and a cryptographic application- due to their distinct features. Our results demonstrate that these customized processors utilize significantly less hardware resources than those required by Xilinx MicroBlaze with reasonable performance degradation using HLS generated hardware exclusively.