Design technique for regulated cascode transimpedance amplifier using Gm/ID methodology

Abstract

This paper presents an approach using gm/ID methodology for the design of the regulated cascode circuit (RGC) transimpedance amplifier (TIA) for optical receivers. The framework uses lookup tables produced using the gm/ID methodology to define the sizing of the transistors needed to reach the required specifications. The presented framework has the advantage of setting limits on the design space using intuitive equations derived from the circuit analyses. This gives insight into the effect of changing the value of different circuit parameters on the resulting design performance while decreasing the calculation time to reach the desired design. The proposed method can reach the required specifications with the flexibility to minimize the DC power consumption or the total input referred noise. The framework is implemented in a 130 ​nm CMOS process with a 1.5 ​V supply voltage producing two different designs. Both designs met the required specifications while optimizing power consumption or noise and were validated using simulations. The results obtained are discussed and compared against other similar designs from the state-of-the-art.