Design Space Exploration of Distributed On-Chip Voltage Regulation Under Stability Constraint

Abstract

Integrating multiple on-chip voltage regulators in a power delivery network (PDN) can offer promising improvements in both voltage regulation and power efficiency. However, the complex interactions between active regulators and the surrounding parasitic passive network create a large number of feedback loops and thus cause stability concern for the distributed regulation network. The recently emerged PDN design methodology based on the hybrid stability theory (HST) provides a unique opportunity for taming the complex PDN stability problem. However, the HST-based stability margin is unfamiliar to circuit designers, and therefore stability-constrained design intuitions are derivable. In this brief, our systematic analysis reveals unique design considerations which can significantly impact the system-level stability and performances. Within a large design space, a comprehensive set of design studies are conducted to shed light on the tradeoffs between the HST-based stability margin and other PDN design specifications such as the quiescent current consumption, maximum switching noise, and area overhead. Useful design insights like how regulator topology, passive decoupling capacitance, and the number of on-chip regulators may be optimized for improved tradeoffs between stability and system performance are discussed. These insights can aid circuit designers to make appropriate design choices at the beginning of the design process for improved system tradeoffs.