Design, simulation, and process development for 2.5D TSV interposer for high performance processer packaging

Abstract

TSV (Through Silicon Via) is regarded as the key enabling technology for 2.5D and 3D IC packaging solution. Si interposers with TSV have emerged as an excellent solution providing high wiring density interconnection, minimizing CTE mismatch to the Cu/low-k chip that is vulnerable to thermo-mechanical stresses, improving electrical performance and decreasing power consumption due to shorter interconnection from the chip to the substrate. This paper presents the design, simulation, and process development of a large TSV interposer for a 18×16 mm test chip with more than 9000 bumps on a flip chip ball grid array (BGA) package. The development of key fabrication steps for the interposer based on 8 inch wafer was supported by process simulation and mechanical stress analysis. The size of the developed interposers is 22×20×0.12 mm with 2 redistribution layers (RDL) on the top side and Cu/Sn pillar bumps on the underside. The assembly process for the TSV interposer and the large die was also developed.