Design, simulation, and investigation of basic logic gates by using NAND logic gate

Abstract

The NAND logic gate is one of the universal logic gates. We can use it to design and build a digital logic gate like (not, and, or) gates. This paper gives Design, Simulation, and Investigation of Basic gates by utilizing NAND Gate with perfect output logic standards with preserving similar performance for all digital logic in this design, we can use it easily to create very large scale integration(VLSI)designing. In our simulation has been tested on the hspice program at 32 nm CMOS technology. The results show this design has low lower dissipation and delay when compared with other designs. When compared to some of these designs, the findings reveal that the intended gate is typically quicker, shorter, and with much less energy dissipation, and there is an increase in speed and power dissipation since the processing technology improves 32nm. In addition, the suggested 4T was shown to be faster than others. In comparison to the typical CMOS NAND gate, which employs some transistors, the suggested design has provided a fresh new structure for creating a two-input NAND gate utilizing just four transistors. The suggested design gate can predict the creation of devices with significantly improved speed, energy consumption, and computationally efficiency.