Design Parameters and Practical Considerations in the Two-Phase Forced-Convection Cooling of Multi-Chip Modules

Abstract

Forced-convection boiling was investigated with a dielectric coolant (FC-72) in order to address some of the practical issues related to the two-phase cooling of multi-chip modules. The module used in the present study featured a linear array of nine, 10 × 10 mm2, simulated microelectronic chips which were flush-mounted along a 20-mm wide side of a rectangular channel. Experiments were performed with a 5-mm channel gap (distance between the chip surface and the opposing channel wall) at eight orientations spaced 45 degrees apart. Two other channel gaps, 2 and 10 mm, were tested in the vertical up flow configuration. For all these configurations, the velocity and subcooling of the liquid were varied from 13 to 400 cm/s and 3 to 36°C, respectively. Changes in orientation did not affect single-phase or nucleate boiling characteristics, but did have a major impact on CHF. Upflow conditions were found to be the best configuration for the design of two-phase cooling modules because of its inherently stable flow and relatively high CHF values. The CHF value for the most upstream chip in vertical upflow agreed well with a previous correlation for an isolated chip. Combined with the relatively small spread in CHF values for all chips in the array, this correlation was found to be attractive for design purposes in predicting CHF for a multi-chip array. To achieve a given CHF value, it is shown how the strong CHF dependence on velocity rather than flow area allows for a reduction in the required flow rate with the 2-mm, as compared to the 5-mm gap, which also required a smaller flow rate than the 10-mm gap. This reduction inflow rate was significant only with subcooled conditions corresponding to high CHF values.