Design Optimization of Photovoltaic Cell Stacking in a Triple-Well CMOS Process

Abstract

Various self-powered devices employ energy-harvesting technology to capture and store an ambient energy. The photovoltaic (PV) cell is one of the most preferred approaches due to its potential for on-chip integration. Although serial connection of multiple PV cells is commonly required to obtain a sufficiently high voltage for circuit operation, a voltage boosting with serially stacked PV cells is limited in a standard bulk CMOS process because all the PV cells are intrinsically connected to the common substrate. It is possible to increase the output voltage by stacking multiple PV cells with a large area ratio between stages. However, nonoptimal design results in a poor conversion efficiency or a limited open-circuit voltage, making it unsuitable for practical applications. This article proposes a stacking structure and its optimal design method for PV cell stacking in a triple-well CMOS process. The proposed approach utilizes an additional current-sourcing photodiode and an optical filter, which allow high voltage generation without a significant efficiency degradation. The test chip with four-stage stacked PV cells was fabricated using a 0.25- $\mu \text{m}$ standard triple-well CMOS process. The experimental results demonstrate an output voltage of 1.6 V and an electrical power of 263 nW/mm2 under an incident illumination with an intensity of $96~\mu \text{W}$ /mm2, achieving a responsivity of 1.91 mA/W and a conversion efficiency of 0.27%.