Design of Universal logic gates and Majority Gate Using One clock pulse based CMOS Capacitor Coupled Threshold Logic

Abstract

In this era of rapid advancement in IC technology, multi-valued logic is playing a bigger role in incorporating multiple functions within single block. Threshold logic gate using Capacitor coupling logic is one of the most effective methods which has given fruitful results. This research paper presents one capacitor coupling logic (C3L) circuit with one clock pulse to implement the CMOS based threshold logic gates .All the simulations are carried out in TANNER software(T spice) using 250nm technology. Here NOR, NAND, AND, OR and majority gate have been designed using this CCLG(Capacitor Coupling Logic Gate) by changing the value of a reference voltage.