Design of Two-Tone RF Generator for On-Chip IP3/IP2 Test

Abstract

In this paper a built-in-self-test (BiST) aimed at the third and second intercept point (IP3/IP2) characterization of RF receiver is discussed with a focus on a stimulus generator. The generator is designed based on a specialized phase-lock loop (PLL) architecture with two voltage controlled oscillators (VCOs) operating in GHz frequency range. The objective of PLL is to keep the VCOs’ frequency spacing under control. According to the test requirements the phase noise and nonlinear distortion of the two-tone generator are considered as a merit for the design of VCOs and analog adder. The PLL reference spurs, critical for the IP3 measurement, are avoided by means of a frequency doubling technique. The circuit is designed in 65 nm CMOS. A highly linear analog adder with OIP3 > +15 dBm and ring VCOs with phase noise < −104 dBc/Hz at 1 MHz offset are used to generate the RF stimulus of total power greater than −22 dBm. In simulations a performance sufficient for IP3/IP2 test of a typical RF CMOS receiver is demonstrated.