Abstract
The latest-generation IBM Z processor provides enhanced performance and compute capacity compared to its IBM z13 predecessor. This paper describes some of the major improvements that include an additional perceptron branch predictor, a completely redesigned translation engine that is tightly integrated into the core pipeline, and an integrated level-1 cache directory and translation lookaside buffer design. Outside of the central processing unit (CPU), the cache sizes have increased on each cache level, and each processor chip now contains 10 CPUs. The system topology has been optimized to improve cache transfer latencies for workloads spanning multiple processor chips. The bus interfaces between the chips have been redesigned to improve peak bus traffic handling. In combination, these enhancements provide significant performance improvements in traditional data-serving workloads, as well as in virtualized Linux environments running database, analytic, and cognitive workloads.
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