Design of tapered serial chains for reduced delay and power dissipation

B.S Cherkauer,E.G Friedman

doi:10.1109/mwscas.1994.519183

Design of tapered serial chains for reduced delay and power dissipation

B.S Cherkauer, E.G Friedman

https://doi.org/10.1109/mwscas.1994.519183

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Publication Date: Aug 3, 1994

Citations: 1

Affiliation: University of Rochester

#Fabricated Test Structures #Serial Chains + Show 8 more

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Abstract

In this paper, the design issues relating to channel width tapered serially connected MOSFET chains are discussed. Channel width tapering is a method which is used to reduce the delay, area, and power dissipation of serial MOSFET chains. A design system for determining when tapering is appropriate, selecting the amount of tapering, and synthesizing the physical layout is presented. Physical layout issues unique to tapering are discussed, and fabricated test structures are described.

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