Design of small volume and low power consumption logic gates based on 4-terminal multilevel magnetic cell

Abstract

Spintronics is an emerging technology for designing logic circuits. The non-volatile logic based on the magnetic tunnel junction (MTJ) cell is a suitable solution to overcome the leakage power problem, which has become a major obstacle for CMOS technology. Here, we introduce a new style of magnetic gate (mGate) logic, which is built by a four-terminal cell. This cell operated by motion of domain wall that is based on spin transfer torque (STT) in a multi-level cell (MLC) structure. To reduce the complexity, a static circuit with a resistive load in ratioed logic style has been used. The use of MLC Gate logic in the static ratioed logic circuit is a suitable solution to reduce the complexity level of structure and power consumption in logic circuits in the field of spintronics. The performance of different magnetic logic gates have been investigated by simulations. The simulation results show that the MLC Gates offer a smaller area and lower power consumption and lower energy in comparison with the previous mGate and magnetic computing in memory.