High-Performance Computing-in-Memory Architecture Based on Single-Level and Multilevel Cell Differential Spin Hall MRAM

Abstract

Computing-in-memory (CiM) architectures have experienced faster growth with the emergence of nanoscale magnetic tunnel junction (MTJ) spintronic devices due to their nonvolatile and CMOS compatible architectures. Recently, spin-transfer torque (STT) and spin Hall effect (SHE)-based several CiM designs have been published. The majority of these designs employ a single-level cell (SLC) memory array and require high write energy to perform logic computations. To mitigate these problems, we propose novel SLC and multilevel cell (MLC) differential spin Hall (DSH) magnetic random access memory (MRAM)-based CiM designs that employed MTJs with field-free switching technique using the in-plane magnetic (IPM) layer. Initially, SLC DSH-MRAM-based magnetic full adder (MFA) is proposed. Furthermore, DSH-MRAM series MLC (sMLC)-based CiM implementations of AND/OR/XOR gates and 1 bit MFA are presented in this work. This DSH-sMLC-based CiM structure exploits a reconfigurable precharge sense amplifier (RPCSA) and innovative MTJ reference mechanism to perform each of the logic operations within a single evaluation cycle and provides complementary logic outputs useful for further computations. The comparative performance analysis of the proposed CiM MFA with SHE-based and voltage-controlled SHE-sMLC-based CiM designs reveals 52% and 33% improvement in write energy, respectively. The proposed design saves 34% area compared to the SHE-based counterpart.