Design of Single Supply and Current Mirror-Based Level Shifter with Stacking Technique in CMOS Technology

Abstract

The paper presents a new design for low power application of single supply and current mirror-based level shifter which is a 45 nm CMOS technique. Those recommended circuits use the benefits for Stacking technique with smaller leakage current and reduction in leakage power. The circuit is deliberate using 45 nm CMOS method. The modified stacking structure is more appropriate to system for high voltage supply. In such SoC’s, level shifters play an important part in translating the signals from one voltage level to another. Single supply level shifter has been modified with two additional NMOS transistors. Another circuit, current mirror level shifter (CMLS) has been modified with three additional NMOS transistors. Performances of the proposed level shifters are compared in terms of power, noise, and leakage parameters. For single supply and current mirror-based level shifter, Supply voltage VddH is initialized as 0.7 V and VddL is initialized as 0.2 V.