Abstract
One of the most important issues in deep nanoscale regime CMOS circuits is related to the time-dependent performance degradation caused by negative bias temperature instability (NBTI). The integration of online aging sensor is becoming attractive methodologies in monitoring performance degradation of circuit. The sensor can generate a warning signal, early warning of the occurrence of aging faults, to avoid unnecessary losses. To accurately capture the aging fault, a real-time aging sensor is proposed with mirror extraction setup and hold (SH) time method. The proposed aging sensor, which is on the basis of the standard flip-flop (FF), consists of an additional edge detector circuit, a detection window generator circuit, and an output warning circuit. Having the adaptive characteristic of detection window, aging sensor is able to adjust its NBTI effects and improve the stability. Also, the sensing network supports multiple paths online detection from many SH sensors for IP chip applications. Finally, the Camellia IP layout is inserted with 20 aging sensors and is implemented under 65-nm CMOS process. Experimental results demonstrate the effectiveness of area, power, and performance overheads. Compared with other state of the art, hardware efficiency is increased by 46%, and energy is decreased by about 37%.
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