Design of self-bias tail transistor technique for low phase noise CMOS VCO with harmonic suppression using capacitance ground

Abstract

This paper presents a low phase noise wideband CMOS VCO based on the self-bias tail transistor technique and harmonic suppression using a capacitance ground. This VCO utilizes switching capacitor arrays in which four channels are able to be selected for multi-band application. Moreover, the design of CMOS VCO makes good use of the self-bias tail transistor and capacitance ground filter technique to reduce the phase noise. The MOS varactors are used as fine tuning for wideband operating application. The fully integrated VCO provides excellent performance with high FOM −193dBc/Hz. The bandwidth of the frequency is 1.1GHz and the tuning range is 13.8%. The power dissipation of the core circuit is 8.28mW under a 1.8V supply and phase noise is measured as low as −123.6dBc/Hz at 1MHz offset under 8.5GHz oscillation frequencies. This VCO was made by the TSMC 0.18μm 1P6M CMOS standard process and the chip area is 0.75×0.69 (mm2).