Abstract
In order to meet the requirements of an Internet of Things (IoT) application with high capacity data storage, a 64M bit resistive random access memory (RRAM) has been designed and fabricated successfully using 180 nm Silterra technology. In the design, the memory cell adopts the one-transistor-one-resistor (1T1R) structure and the layout of the memory cell is optimized to minimize the chip area. In order to maximize the performance of the RRAM, the method of split array and hierarchical decoding are adopted in the circuit design. To ensure the correct readout of data, 32 reference word lines can be connected with different reference resistors to generate appropriate reference current while the sense amplifier (SA) circuit is specially designed to achieve fast data readout. Using this circuit we achieved a measurement result for the 64M bit RRAM chip, the read access time is less than 20 ns, the data retention time is more than 10 years, and the endurance is more than 107 cycles.
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