Design of prominent Time-to-Digital Converter using single electron transistor operating at room temperature

Abstract

Single electron transistor (SET) has the potential for low power applications due to its low power consumption and high performance. In this paper, we have proposed a novel implementation of fully digital Time-to-Digital Converter (TDC) using single electron transistor and 16nm CMOS FINFET technology. A delay line based, 8-bit resolution TDC is implemented. The proposed SET based TDC has 49.7% power consumption improvement over 16nm CMOS technology. Performance of SET based TDC is also compared and found to be better than the CMOS based implementation. The design is implemented in CADENCE virtuoso design environment. Although the SET has low driving capabilities there are many alternatives ways to improve it at the cost of power and area. Since SET is power and area efficient, trade-offs would not be an issue for highly complex digital designs. SET is a futuristic device and has many aspects to explore in the future.