Design of power-efficient pipelined truncated multipliers with various output precision

Abstract

An energy-efficient multiplier is very desirable for multimedia and digital signal processing systems. In many of these systems, the effective dynamic range of input operands for multipliers is generally limited to a small range and the case with maximum range seldom occurs. In addition, the output products of multipliers are usually rounded or truncated to avoid growth in word size. Based on these features, a low-power signed pipelined truncated multiplier is proposed that can dynamically detect multiple combinations of input ranges and deactivate a large amount of the unnecessary transitions in non-effective ranges to reduce the power consumption. Moreover, the proposed multiplier can trade output precision against power consumption so as to further reduce power consumption. Experimental results show that the proposed multiplier consumes up to 90% less power than the conventional standard multiplier while still maintaining an acceptable output precision and quality.