Design of optimal nano-CMOS differential VCO for RF applications

Abstract

In the design of radio frequency (RF) circuits fast prototyping with optimal performance is a challenging task for designers. The noise consideration in the differential voltage controlled oscillator (DVCO) is very much vital in its design. The present work focuses on the design of low phase noise and low power robust nano-CMOS differential voltage controlled oscillator (DVCO) for a desired frequency of oscillation 2.4 GHz. Constrained multi-objective optimisation, infeasibility driven evolutionary algorithm (IDEA) is used to minimise the phase noise and power consumption simultaneously. In this work, the phase noise is formulated to inherently account for the flicker noise along with the thermal noise and optimised along with power consumption by IDEA. The optimal performing circuit is synthesised using GPDK-90 nm 1P9M process library. The frequency of oscillation obtained in the parasitic inclusive design of the differential VCO is 2.399513658 GHz which is in good agreement with the target frequency with negligible deviation and the corresponding optimum values of power consumption and phase noise recorded are 845.5095 µW and 79.67 dBc/Hz at 1 MHz offset, respectively.