Design of New Multilevel Inverter Topology for Various Unipolar Triangular Carrier PWM Strategies

Abstract

Multilevel inverters have been widely used for high power and high voltage applications as their performance is highly superior to that of conventional two level inverters due to reduced harmonic distortion, lower electromagnetic interference, and higher dc link voltages but it has some disadvantages such as increased number of components, complex pulse width modulation control method and voltagebalancing problem. In order to compensate the above described disadvantages a new topology with a reversing voltage component is proposed to improve the multilevel performance. This topology requires fewer components compared to existing inverters (particularly in higher levels) and requires fewer carrier signals and gate drives. Therefore, the overall cost and complexity are greatly reduced particularly for higher output voltage levels. Finally, a power circuit of the seven-level proposed topology is developed and simulated with different modulation strategies to show the performance of the inverter by simulation results using MATLAB-SIMULINK. By comparing the various Unipolar Pulse Width Modulation (UPWM) techniques, it is observed that UPDPWM provides less THD and UCOPWM techniques provide higher fundamental RMS output voltage. Compared to the conventional MLI’s like DCMLI, FCMLI and CMLI the proposed topology will reduce the number of switches, clamping diodes and clamping capacitors. The proposed topology will have the advantages if the number of levels is increased. The total harmonic distortion will be within IEEE standards. The main object of the proposed topology is to reduce the number of switches compared to conventional MLI’s and to achieve the THD within IEEE standards without any additional filter.