Design of NBTI-resilient extensible processors

Abstract

In this paper, we present techniques for mitigating the Negative Bias Temperature Instability (NBTI) effect on extensible processors. Firstly, the effect of NBTI on the extended instruction set architecture and the arithmetic logic unit of extensible processors is studied. The study includes modeling the circuit delay increase due to the NBTI and analyzing its impact on the processor lifetime. The study shows that in some cases, the lifetime is decreased while in other cases, it is increased compared to that of a baseline processor. Next, to lower the impact of the NBTI on the extensible processor lifetimes, we present four different techniques. The first technique is based on injecting proper input vectors during the idle time of the custom instructions such that the NBTI effect is reduced. The lifetime improvement, however, is limited by the delay increase reduction of the applied input vectors. In the second technique, the guard band delay of extensible processor is extended. This is effective because the rate of lifetime increase due to extending the guard band delay is much higher than the rate of speedup reduction. For the third technique, we duplicate the critical custom instructions to increase the processor lifetime without losing any speedup. The last technique estimates the delay increase of candidate custom instructions (CIs) and selects those that do not reduce the lifetime. The efficacies of the aforesaid techniques are evaluated and compared against each other by using benchmarks from different application domains.