Design of multiple RESURF LDMOS with P-top rings and STI regions in 65nm CMOS technology

Abstract

In this work, a novel multiple RESURF P-top rings LDMOS with shallow trench isolation (STI) structure based on the 65 nm baseline low-voltage CMOS technology by three-dimensional Sentaurus process and device simulations. A optimized uniform electric filed distribution in N-drift region can be obtained by employing the multiple P-top rings process instead of the past proposed gate field plates method in the extended drain regions. By this way, not only both of high breakdown voltage exceeded over 40V and low on-resistance below 20 mΩ-mm2 can be achieved, but also the effect of W N-drift /W STI ratio on device can be reduce to obtain the larger optimal window of device characteristics, as compared with the conventional DIELER and graded gate field plate devices.