Design of Low-Power Full Adder Using Two-Phase Clocked Adiabatic Static CMOS Logic

Abstract

In this paper, a full adder using two-phase clocked adiabatic static CMOS logic (2PASCL) has been presented. A six-transistor X-OR gate has been used with transmission gate multiplexer. The simulations of proposed and other designs have been performed in 0.18 µm CMOS technology. The proposed design shows improved power delay product (PDP) in the range of \(0.34\, \times \,10^{ - 21} \,{\text{J}}\) to \(1.12\, \times \,10^{ - 21} \,{\text{J}}\) as compared to \(4.53\, \times \,10^{ - 21} \,{\text{J}}\) to 6.7 \(8\, \times \,10^{ - 21} {\text{J}}\) (static energy recovery full adder), 3.4 \(1\, \times \,10^{ - 21} \,{\text{J}}\) to \(7.36\, \times \,10^{ - 21} \,{\text{J}}\) (10 transistor), \(6.40\, \times \,10^{ - 21} \,{\text{J}}\) to \(19.17\, \times \,10^{ - 21} \,{\text{J}}\) (transmission gate) with a supply voltage variation of 1.2 V–2.8 V respectively. The proposed design also performs better at varying temperature conditions as compared to other existing designs. Simulation results of proposed design have been compared with existing designs reported in the literature and proposed design shows better performance in terms of PDP.