A Low Power and High Speed 8-bit ALU Design using 17T Full Adder

Abstract

In this paper, a novel 17T full adder and its application in implementing an efficient Arithmetic Logic Unit (ALU) design have been proposed. The proposed design will be able to significantly reduce the power requirements of a digital processor. Further, it also minimizes the delay and the design is efficient in terms of power-delay product. The ALU is one of the important entities of a digital processor. In a digital processor, an ALU as the name suggest performs logical and arithmetic operations. Thus, increasing the speed of operation while reducing the power requirements can cause a cumulative increase in the throughput of the digital system. Further, the proposed 17T full adder uses only multiplexing logic to produce the Sum and the Carry-Out signals with similar Sum and Carry-Out signal path delay. Moreover, the signal propagation delay from input to output of the proposed adder has been found to be 83.8% to 89.9% less as compared to existing hybrid full adder design like HFA-22T, HFA-20T and HFA-19T as well as full adders like 10T and 11T. Further, 71.5% to 74.3% saving in power requirements has been observed. Thus, the proposed 8-bit ALU has also been able to perform almost 52% better than the existing design in terms of the overall power-delay product. We have simulated the designs as well as evaluated the results using the Cadence Virtuoso EDA tool v15.0 in 45 nm process technology. Performance analyses were done with respect to power, delay, and power-delay product.