Design of Low Voltage Low Power OP-AMP using DTMOS Technique

Abstract

ABSTRACT This paper demonstrates the design of low voltage, low power CMOS op-amp using DTMOS technique for low-power applications. The design goal is to achieve high gain, phase margin and minimum power dissipation at lower supply voltage. DTMOS transistor is proposed in this paper for the design of op-amp which replaces the normal CMOS transistors for designing a low power, low voltage two stage op-amp. A dc gain of 96.38 dB, a phase margin of 71.46o by achieving a unity gain bandwidth of 4.077 MHz while operating at 1V supply voltage. The performed simulation results show a power dissipation of 12.19 µW is achieved under 5 pF load in this design. The design and analysis is performed using 180 nm CMOS technology in Cadence Virtuoso ADE . Keywords Low power applications, Diff-amp, op-amp, DTMOS, Low power, Low voltage . 1. INTRODUCTION From the past few years due to the extensive growth of market for portable devices such as cell phones, portable computers, other low power applications and also the design of analog circuits which requires low power, low voltage with high performance has become an important issue now a day’s [2]. One of the limitations for implementation of portable devices and design of other low power circuits at low voltage is the threshold voltage (V