Design Of Low Power Two Stage Op-Amp Using Sub-20 nm CMOS Technology

Abstract

An Operational amplifier is one of the most versatile and fundamental building block in almost every analog and mixed signal processing circuits.The design of analog and mixed signal system is always a challenging task. Nowadays researches are being carried out in the field of scaling down the CMOS devices so that their area and power consumption can be reduced. This paper presents the design of a two stage Op-Amp using sub20 nm CMOS technology. This design has a differential amplifier stage and an additional gain stage, implemented with minimum number of transistors, so that the area and power consumption is optimized. Design and simulation was done using cadence EDA software tool. The designed Op-Amp is operating with a supply voltage of 800 mV and a bias current of 10µA.The design attains an open loop gain of 88.74dB with unity gain bandwidth of 50.7 MHz and a phase margin of 57.98 degree with load capacitor of 1 pF. The average power consumption of the amplifier is found to be 533µW and the slew rate is 20V/µs.