Design of low power standard cells using full swing gate diffusion input

Abstract

The key success factor for the rapid growth of the integrated system is the use of ASIC library for various system functions. Different Integrated Circuits (IC) implementation approaches have been used to reduce the design time and improve manufacturing costs. One of the method is designing Cell Based IC implementation approach using standard cell libraries. The performance of the design is depends on the quality of standard cells used in the design. Hence designing low power, high speed standard cells plays an imported role in the system design. In this paper standard cells are created using Gate Diffusion Input (GDI) technique which gives better result than CMOS standard cells in terms of power, area and delay. The standard cells are characterized using Liberate tool from the Cadence and used in full adder design using verilog code. Comparing the CMOS and GDI standard cells result in terms of power, area and delay.