Abstract
Design of Low Power Phase Locked Loop (PLL) Using 45NM VLSI Technology
Highlights
The electronics industry has achieved a phenomenal growth over the last two decades, mainly due to the rapid advances in integration technologies, large-scale10.5121/vlsic.2010.1201systems design - in short, due to the advent of VLSI [1]
Basic Phase locked loop Analog PLLs are generally built of a phase detector, low pass filter and voltagecontrolled oscillator (VCO) placed in a negative feedback configuration as shown in fig
This paper describes the improvement related to the CMOS 45nm technology and the implementation of this technology in Microwind 3.1
Summary
The electronics industry has achieved a phenomenal growth over the last two decades, mainly due to the rapid advances in integration technologies, large-scale. The PLL uses a high frequency oscillator with varying speed, a counter, a phase detector and a filter. Basic Phase locked loop Analog PLLs are generally built of a phase detector, low pass filter and voltagecontrolled oscillator (VCO) placed in a negative feedback configuration as shown in fig.. Since initially the oscillator may be far from the reference frequency, practical phase detectors may respond to frequency differences, so as to increase the lock-in range of allowable inputs. A phase locked loop (PLL) with a single voltage controlled oscillator (VCO) is generally configured to lock multiple internal clocks to multiple incoming data signals of different frequencies. The rapid variations of the phase detector output are converted into a slow varying signal VC by filter, which will later control the voltage controlled oscillator. Besides this charge pump circuits will be used to convert digital error pulse to analog error current
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