A Hybrid Divide—16 Frequency Divider Design for Low Power Phase Locked Loop Design

Supraja Batchu,Ravi Nirlakalla,Jayachandra Prasad Talari,Venkateswarlu Surisetty

doi:10.1007/978-81-322-2671-0_47

A Hybrid Divide—16 Frequency Divider Design for Low Power Phase Locked Loop Design

Supraja Batchu, Ravi Nirlakalla + Show 2 more

https://doi.org/10.1007/978-81-322-2671-0_47

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Publication Date: Dec 29, 2015

Citations: 7

#Low Power Phase Locked Loop #Power Phase Locked Loop + Show 8 more

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Abstract

In this paper, we present a divide by 16 frequency divider (FD) for high frequency and low power phase locked loop (PLL) designs. The FDs have shown efficiency in different parameters. Divide by 16 FDs are proposed with a hybrid model which combined with a true single-phase clock (TSPC) and E-TSPC for low power PLL. Results of FDH1 have shown low power consumption.

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