Abstract
New low-power Level Shifter (LS) circuit is designed by using sleep transistor with Multi Threshold CMOS (MTCMOS) technique for robust logic voltage shifting from sub-threshold to above- threshold domain. MultiSupply Voltage Design (MSVD) technique is mainly used for energy and speed in modern system-on-chip. In MSVD, level shifters are required to allow different voltage supply to shift from the lower power supply voltage to the higher power supply voltage. This new low-power level shifter circuit is also used for fast response and low leakage power consumption. This low leakage power consumption can be achieved through insertion of sleep transistor and proper transistors sizing. The proposed design efficiently converts 100 mv input signal into 1 v output signal and achieves the power of 2.56 nW by using 90 nm technology.
Highlights
Voltage Domain (MSVD) technique is an effective method to reduce both dynamic and leakage powers in modern system-on-chips
Time critical domains run at higher power supply voltage (VDDH) to maximize performance, while noncritical domains run at lower power supply voltage (VDDL), to reduce static and dynamic power without impacting on the overall circuit performance
The proposed low power level shifter is mainly used for power reduction and wide range voltage conversion in MultiSupply Voltage Domain
Summary
Voltage Domain (MSVD) technique is an effective method to reduce both dynamic and leakage powers in modern system-on-chips. A two-stage LS was proposed, the first stage exploits a DCVS circuit with an always-on diode-connected nMOS transistor on the top; whereas, the second one is a conventional DCVS stage that achieves rail to rail swing It avoids intermediate power lines, but again it is not enough to reach high-speed performances. The LS was designed by two pMOS current limiters to reduce the half-latch pull-up strength within the conventional DCVS structure This circuit is able to convert subthreshold input signals and it requires reasonably sized pulldown transistors. A circuit based on current mirrors has been designed for better speed performance, but the current mirror output floats when the input voltage signal is high [10]-[12] This causes a detrimental effect on subthreshold leakage of the output buffer.
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