Design of Low Power Digital FIR Filter based on Bypassing Multiplier

Abstract

Low power design promotes longer battery life in portable applications and reduces heat dissipation in high performance applications. Multiplication is one of the important operations in digital signal processing and their power dissipation is the prime concern. Many earlier multiplier designs were analyzed to reduce the switching transition. Bypassing technique is mainly used to reduce the switching power of the multiplier. Various bypassing multipliers such as Row bypassing, Column bypassing, Two-dimensional bypassing and RowColumn bypassing based multipliers were designed based on the simplification of the incremental adders and half adders instead of full adders in an array multiplier. In these multipliers extra correction circuits are required to obtain accurate results. The extra hardware in conventional design results in more power consumption. So, to overcome the drawback of conventional methods, the proposed low power bypassing based multiplier uses a simplified addition operation to reduce the switching activity and it achieves 38.7% and 25.2% of area and power reduction respectively. By taking the advantage of low power bypassing based multiplier, a digital FIR filter is implemented. The experimental results show that our proposed low power digital FIR filter saves 51% and 7% of area and power reduction respectively by using low power bypassing based multiplier. General Terms VLSI design.