Design of low phase noise and area-efficient PLL in microwave generation and intelligent control

Abstract

An integer-N phase-locked loop (PLL) is designed and fabricated in TSMC 0.18-um CMOS technology. The proposed PLL with a complementary crossed-couple LC-tank voltage-controlled oscillator (VCO) and a mixed design of current mode logic (CML) and true single phase clock (TSPC) logic in the frequency divider achieves a fiber lasers application in microwave signal generation and intelligent computing from a free running mode-locked Er-fiber laser. In the stretched-pulse regime, the Er-fiber laser is designed at close-to-zero dispersion to minimize the phase noise of extracted microwaves. In order to suppress the excess phase noise in the optical to electronic conversion process, we synchronize a low-noise PLL to the fiber laser using a fiber Sagnac-loop-based optical-microwave phase detector.