Design of Low Leakage Arithmetic Logic circuit Using Efficient Power Gating Schemes

Abstract

As technology scales towards nanometer regime the leakage power consumption emerging as a major design constraint for the analysis and design of complex arithmetic logic circuits. In this paper, comparative analysis of standby leakage current and sleep to active mode transition leakage current has been done. An innovative power gating approaches is also analyzed which targets maximum reduction of major leakage current. To analyze we introduce the stacking power gating scheme, we implemented this scheme on carry look ahead adder circuit and then simulation has been done using stacking power gating scheme with 45nm technology parameters. The simulation results by using this scheme in BPTM 45nm technology with supply voltage of 0.9V at room temperature shows that leakage reduction can be improved by 47.14% as on comparison with single transistor gating scheme on comparing with conventional scheme Also, another novel approach has been analyzed with diode based stacking power gating scheme for further reduction in leakage power. The simulation results depicts that the analyzed design leads to efficient carry look ahead adder circuit in terms of leakage power, active power and delay.