Design of large high-speed floating-point-arithmetic units

Abstract

An investigation of the design philosophy of large floating-point -arithmetic units has been undertaken, with a view to establishing the principles for constructing such a unit for a large high-speed computing system. The main consideration applied was maximum speed for a reasonable cost in a machine handling numbers 30–64 bits in length. Consideration of compatibility with other systems was specifically excluded, although the unit to be implemented does take this factor into account. Within these constraints, it is shown that negative numbers should be represented in twos-complement form. Numbers of upto 64 bits in length would be handled, with the binary point at the less significant end of the mantissa. Rounding should be performed by forcing a ‘carry in’ to the least significant bit when the answer is more than single length, sufficient information being retained to enable multilength arithmetic to be implemented. Answers should not be normalised. The data presented are sufficient to indicate the effect of applying different criteria.