Abstract
In this paper, a high throughput low-density parity-check (LDPC) decoder for 802.16e standard is presented. With simultaneous rows and columns processing, which reduced the number of clock cycles per iteration, the throughput of the decoder is improved. The proposed decoder architecture was designed for 802.16e standard with rate of 1/2 and code length of 2304 with 7-encodings style. It is synthesized on 130 nm CMOS technology by Synopsys Design Compiler. The obtained result in the operating frequency of 100 MHz shows total power consumption of 242mW and the chip area of 6.9 mm2.
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