Design of High-Speed Adders for Efficient Digital Design Blocks

Akansha Baliga,Vijaya Krishna A,Deepa Yagain

doi:10.5402/2012/253742

Abstract

The core of every microprocessor and digital signal processor is its data path. The heart of data-path and addressing units in turn are arithmetic units which include adders. Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are well suited for VLSI implementations. This paper involves the design and comparison of high-speed, parallel-prefix adders such as Kogge-Stone, Brent-Kung, Sklansky, and Kogge-Stone Ling adders. It is found that Kogge-Stone Ling adder performs much efficiently when compared to the other adders. Here, Kogge-Stone Ling adders and ripple adders are incorporated as a part of a lattice filter in order to prove their functionalities. It is seen that the operating frequency of lattice filter increases if parallel prefix Kogge-Stone Ling adder is used instead of ripple adders since the combinational delay of Kogge-Stone Ling adder is less. Further, design and comparison of different tree adder structures are performed using both CMOS logic and transmission gate logic. Using these adders, unsigned and signed comparators are designed as an application example and compared with their performance parameters such as area, delay, and power consumed. The design and simulations are done using 65 nm CMOS design library.

Highlights

Binary addition is one of the most primitive and most commonly used applications in computer arithmetic
Schematic is constructed for 8 bit and 32 adders using CMOS and transmission gates as given in Figures 10, 11, 12, 13, and 14
Measurement of power, area, and delay is done. This can be done by designing the basic components such as black and grey cells using CMOS and transmission gates

Summary

Introduction

Binary addition is one of the most primitive and most commonly used applications in computer arithmetic. Parallel-prefix adder tree structures such as Kogge-Stone [4], Sklansky [5], Brent-Kung [6], Han-Carlson [7], and Kogge-Stone using Ling adders [8, 9] can be used to obtain higher operating speeds. For wide adders (N > 16), the delay of carry look-ahead adders becomes dominated by the delay of passing the carry through the look-ahead stages This delay can be reduced by looking ahead across the look-ahead blocks. We can construct a multilevel tree of look-ahead structures to achieve delay that grows with log N. Such adders are variously referred to as tree adders or parallel prefix adders. Adder components are designed, analyzed, and compared using CMOS gates

Methods

Results

Conclusion