Design of High-Voltage-Tolerant ESD Protection Circuit in Low-Voltage CMOS Processes

Abstract

Two new electrostatic discharge (ESD) protection design by using only 1 times VDD low-voltage devices for mixed-voltage I/O buffer with 3 times VDD input tolerance are proposed. Two different special high-voltage-tolerant ESD detection circuits are designed with substrate-triggered technique to improve ESD protection efficiency of ESD clamp device. These two ESD detection circuits with different design concepts both have effective driving capability to trigger the ESD clamp device on. These ESD protection designs have been successfully verified in two different 0.13-mum 1.2-V CMOS processes to provide excellent on-chip ESD protection for 1.2-V/3.3-V mixed-voltage I/O buffers.