Design of High Stability LDO Based on CMOS Technology

Abstract

This paper presents a low dropout linear regulator (LDO) structure designed by 0.18um CMOS process; it includes the bandgap voltage reference with good temperature characteristic, the error amplifier of high gain and good PSRR, the power adjustment transistor and resistance feedback network which have reasonable sizes, and slew rate enhancement circuit. The circuit simulation and layout design are successfully completed. The experimental results of LDO show that the circuit gain is 99.47dB, the phase margin is 67.27°, and the PSRR is 90.65dB. The linear adjustment rate is 0.3%, the load adjustment rate is 2.7%; the quiescent current is 56.1uA, the temperature drift coefficient is 8.04ppm/°C, and the layout area is 0.04mm2. This design meets the requirements that are low dropout, high stability and small area.