Abstract
Multiplication is essential arithmetic operations for the filter. In this paper, high-speed area-efficient RCA based 2-D bypassing multiplier proposed for finite-impulse response (FIR) filter implementation. Conventional CSA based 2-D bypassing multiplier provides low power in comparison with array multiplier because the number of signal transitions is reduced when the horizontal (rows) and vertical (columns) operands are zero. But the area is increased due to the additional adder and logic cells (multiplexer) used for bypassing technique. The proposed RCA based 2-D bypassing multiplier eliminates the carry multiplexer in all logic cells. Due to this the area has reduced when compared to the conventional CSA based 2-D bypassing multiplier, at the same time the proposed architecture is designed using Divide and Conquer method, so the delay also reduced for the proposed multiplier.
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