Booth Multiplier-Based Robust Model of FIR Filters for VLSI Applications

Abstract

Filters with a finite impulse response, often known as FIR filters, are used widely in a wide variety of digital signal processing applications, including digital audio, image processing, data transmission, biomedical, and many more. In certain applications, the FIR filter circuit must be able to work at high sample rates, while in others, it must perform at low power and moderate sample rates. Both of these requirements must be met simultaneously. Both of these requirements must be met. The design and implementation of FIR filters involve a significant number of multiplications, which results in a significant amount of wasted space and energy. When it comes to the design and implementation of a DSP processor, the most important considerations are the decrease in power consumption and the optimization of the use of available space. The adder, the flip-flop, and the multiplier blocks are the three basic components that come together to form the Finite Impulse Response (FIR) Filter. The output is heavily impacted by the FIR filter, which is responsible for producing the slowest frame of them all. The wait, as well as the field, became longer. It is feasible to develop the FIR Filter for use in VLSI applications that need low voltage and low power. This is made possible by even lower power consumption as well as a decrease in the delay and operating speed of the booth multiplier. This research work presents the Finite Impulse Response Filter and compared the two recommended FIR filters by utilizing a variety of parameters. Two separate multipliers, the Array Multiplier and the Booth Multiplier are employed to accomplish these two tasks.