Abstract
The cross-coupled circuit mechanism based dynamic latch comparator is presented in this research. The comparator is designed using differential input stages with regenerative S-R latch to achieve lower offset, lower power, higher speed and higher resolution. In order to decrease circuit complexity, a comparator should maintain power, speed, resolution and offset-voltage properly. Simulations show that this novel dynamic latch comparator designed in 0.18 µm CMOS technology achieves 3.44 mV resolution with 8 bit precision at a frequency of 50 MHz while dissipating 158.5 µW from 1.8 V supply and 88.05 µA average current. Moreover, the proposed design propagates as fast as 4.2 nS with energy efficiency of 0.7 fJ/conversion-step. Additionally, the core circuit layout only occupies 0.008 mm2.
Highlights
An analog-to-digital converter (ADC) is the vital component to drive the integrated circuit (IC) design industry in recent years. Portable electronic systems such as devices used in the wireless communication, consumer electronics or medical equipments elevates the requirement of producing low–power, high speed circuit methods and building blocks
CADENCE Virtuoso in a 0.18 mm CMOS process parameter is utilized in this design
A novel high-speed, low power and low offset dynamic latchtype comparator method is presented in this research works
Summary
An analog-to-digital converter (ADC) is the vital component to drive the integrated circuit (IC) design industry in recent years. CMOS dynamic latch comparators are very popular due to fast-speed, low-power consumption, high-input impedance and full-swing output. To design the latch comparator for low voltage operations, which are capable of reducing the dynamic input ranges and the analogous differential process sometimes elevates the power indulgences in rail-to-rail maneuver [2,8]. A dynamic latch comparator without pre-amplifier is very much enviable for high speed and low power applications. In 2008, a dynamic comparator with a charge pump circuit is proposed to order related input referred offset voltage, which makes the approach inefficient [12]. The proposed design is capable of generating high-speed, high resolution with low power indulgence in low supply voltages compared to the conventional dynamic latch comparators. The simulated results show that, the circuit topology makes it valid to perform under low supply voltage
Sign-in/Register to view highlights & summary Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a call
