Design of high performance power efficient flip flops using transmission gates

Abstract

Flip-flop plays a major role in designing a synchronous circuits and memory. In this paper we have shown the comparison of performance for various circuits of flip flops, master-slave flip flops and transmission gates. FFs are mostly used to collect the group of data for a storage purpose and the performance includes delay, area minimization and power reduction. The delay can be minimized by transistor sizing and variation of voltage. The proposed circuits are simulated and compared using 90nm and 45nm technology.