Design Of High Density Memory Cell Library For Low Voltage Operation In 65nm LSTP Technology

Abstract

In advanced high-performance digital SoCs, embedded SRAMs occupy nearly 70% of die area. Therefore, optimizing SRAMs for density, power consumption, and performance is very important. This paper presents the design of a high-density SRAM memory cell suite comprising of different configurations of IRIW 8T cell and a conventional 6T cell in 65nm low standby power (LSTP) technology node. The effect of using assist schemes to lower minimum operational voltage ($V_{\min}$) of the SRAM cell is evaluated. We show that while at $V_{\min}$=1.08V, a conventional 6T cell is 25% denser than a IRIW 8T cell, at $V_{\min}$=0.81V, 8T cell with write assist is around 7% denser and has 33% lower leakage and better performance than a 6T cell.