Design of gate stacks for improved program/erase speed, retention and process margin aiming next generation metal nanocrystal memories

Abstract

In this work, gate stacks in metal nanocrystal (NC) memories, as promising next generation storage devices and their systems, are extensively investigated. A comparative analysis and characterization of the program/erase (P/E) speed, retention and the process margin of cobalt NC memories including high-k and bandgap engineering technologies are performed by using the technology computer-aided design (TCAD) simulation. It is shown that NC memory with high-k dielectric (HfO2) has better performance in P/E speed and retention when the diameter of NC is below 5 nm. When the diameter is beyond 5 nm, on the other hand, the bandgap-engineered bottom oxide gate structure shows improved performance in P/E speed and retention. From the process margin perspective, as the permittivity of the dielectric gets larger, the limits of the diameter and the density of NCs allow the degree of freedom to become larger.